Implementation of ReBISR Scheme for RAMs using Spare Elements
DOI:
https://doi.org/10.51983/ajeat-2013.2.1.646Keywords:
Memory built-in self test (MBIST),, Built-in redundancy analysis (BIRA), Writing0/ writing1 algorithm, Built-in self repairAbstract
Key components of SOCs are memories which come with different sizes and different configurations. Memories usually constitute a major portion of the chip area. By improving the yield of RAM improves the yield of chip. Diagnostics for yield improvement of the memories thus is a very important issue. This paper presents a Built-in Self Repair scheme to repair the memories for yield improvement of the chip using redundancy analysis algorithm. The proposed BISR scheme has three phases. In the first phase BIST is used to detect the faulty location in the memory. In order to determine a correct repair solution, spare memories are allocated in the second phase using BIRA circuitry. Finally, in the third phase the actual repair process is carried out using BISR circuitry. Experimental results show that the proposed BISR algorithm achieves optimal repair rate and low area cost.
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