Gowthami, P., and R. V. S. Satyanarayana. “FPGA Implementation of Reversible Adder/Subtractor”. Asian Journal of Engineering and Applied Technology 7, no. 2 (July 8, 2018): 16–20. Accessed November 21, 2024. https://ajeat.com/index.php/ajeat/article/view/1011.