GOWTHAMI, P.; SATYANARAYANA, R. V. S. FPGA Implementation of Reversible Adder/Subtractor. Asian Journal of Engineering and Applied Technology, [S. l.], v. 7, n. 2, p. 16–20, 2018. DOI: 10.51983/ajeat-2018.7.2.1011. Disponível em: https://ajeat.com/index.php/ajeat/article/view/1011. Acesso em: 23 nov. 2024.